Dynamically Self-Reconfigurable Machine Learning Structure for FPGA Implementation

In this paper, we describe organization of a machine learning system based on dynamically reconfigurable architecture and self-organization. This system learns typical neural network tasks using self-organizing learning array algorithm described elsewhere. To develop this system, we adopt hardware-software codesign approach based on combining an array of VIRTEX XCV1000 FPGAs with custom software – Matlab/C++. The prototype structure is divided into hardware architecture, software programs and their interface. Hardware architecture dynamically implements the neurons training and voting. Software programs implement control of database and system level management, and are interfaced with hardware via PCI bus using developed C++ dynamic libraries and interface logic.